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Single Chip Ethernet Controller |
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Dual Speed - 10/100 Mbps |
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Fully Supports Full Duplex Switched Ethernet |
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Supports Burst Data Transfer |
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8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers |
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Enhanced Power Management Features |
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Optional Configuration via Serial EEPROM Interface |
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Supports 8, 16 and 32 Bit CPU Accesses |
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Internal 32 Bit Wide Data Path (into Packet Buffer Memory) |
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Early TX, Early RX Functions |
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Built-in Transparent Arbitration for Slave Sequential Access Architecture |
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Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues |
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3.3V Operation with 5V Tolerant I/O Buffers |
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Single 25 MHz Reference Clock for Both PHY and MAC |
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External 25 MHz Output Pin for an External PHY Supporting PHY's Physical Media |
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Low Power CMOS Design |
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Supports Multiple Embedded Processor Host Interfaces
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ARM |
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SH |
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Power PC |
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Coldfire |
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680X0, 683XX |
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MIPS R3000 |
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3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate |
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MII Management Serial Interface |
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128 Pin QFP Package; Green, Lead-free Package also available |
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128 Pin TQFP Package, 1.0 mm Height; Green, Lead-free Package also available |
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Industrial Temperature Range from -40°C to 85°C (LAN91C111I only) |
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| Network Interface |
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Fully Integrated IEEE 802.3/802.3u - 100BASE-TX/10BASE-T Physical Layer |
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Auto Negotiation: 10/100, Full/Half Duplex |
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On Chip Wave Shaping - No External Filters Required |
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Adaptive Equalizer |
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Baseline Wander Correction |
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LED Outputs (User Selectable - Up to Two LED Functions at One Time)
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Link |
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Activity |
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Full Duplex |
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10/100 |
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Transmit |
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Receive |
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The LAN91C111 is defined to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal analog/digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
