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Single Chip Ethernet Controller |
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Dual Speed - 10/100 Mbps |
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Fully Supports Full Duplex Switched Ethernet |
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Supports Burst Data Transfer |
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8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers |
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Enhanced Power Management Features |
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Optional Configuration via Serial EEPROM Interface |
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Supports 8, 16 and 32 Bit CPU Accesses |
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Internal 32 Bit Wide Data Path (into Packet Buffer Memory) |
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Early TX, Early RX Functions |
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Built-in Transparent Arbitration for Slave Sequential Access Architecture |
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Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues |
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3.3V Operation with 5V Tolerant I/O Buffers |
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Single 25 MHz Reference Clock for Both PHY and MAC |
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External 25 MHz Output Pin for an External PHY Supporting PHY's Physical Media |
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Low Power CMOS Design |
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Supports Multiple Embedded Processor Host Interfaces
 |
ARM |
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SH |
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Power PC |
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Coldfire |
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680X0, 683XX |
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MIPS R3000 |
|
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3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate |
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MII Management Serial Interface |
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128 Pin QFP lead-free RoHS compliant package |
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128 Pin TQFP 1.0 mm height lead-free RoHS compliant package |
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Commercial Temperature Range from 0°C to 70°C (LAN91C111) |
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Industrial Temperature Range from -40°C to 85°C (LAN91C111i) |
| |
| Network Interface |
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Fully Integrated IEEE 802.3/802.3u - 100BASE-TX/10BASE-T Physical Layer |
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Auto Negotiation: 10/100, Full/Half Duplex |
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On Chip Wave Shaping - No External Filters Required |
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Adaptive Equalizer |
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Baseline Wander Correction |
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LED Outputs (User Selectable - Up to Two LED Functions at One Time)
|
Link |
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Activity |
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Full Duplex |
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10/100 |
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Transmit |
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Receive |
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The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
Although the information in this document has been checked and is believed to be accurate, no responsibility is assumed for
inaccuracies. SMSC reserves the right to make changes to product descriptions and specifications at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order. Products may contain design defects or errors known as anomalies which may cause a product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC and the SMSC logo are registered trademarks of Standard Microsystems Corporation ("SMSC"). Other names mentioned may be trademarks of their respective holders. All claims made herein speak as of the date of this material. The company does not undertake to update such statements. (11/08)
