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LPC47N227
100 Pin Super I/O with LPC Interface for Notebook Applications
Features
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3.3 Volt Operation (5V Tolerant) |
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PC99 and ACPI 1.0b Compliant |
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Programmable Wake-Up Event Interface (nIO_PME
Pin) |
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SMI Support (nIO_SMI Pin) |
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GPIOs (29) |
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Two IRQ Input Pins |
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XNOR Chain |
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Intelligent Auto Power Management |
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2.88MB Super I/O Floppy Disk Controller
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Licensed CMOS 765B Floppy Disk Controller |
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Software and Register Compatible
with SMSC's Proprietary 82077AA Compatible Core |
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Supports One Floppy Drive Directly |
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Configurable Open Drain/Push-Pull
Output Drivers |
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Supports Vertical Recording Format |
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16-Byte Data FIFO |
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100% IBM Compatibility |
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Detects All Overrun and Underrun
Conditions |
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Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown Modes for Reduced
Power Consumption |
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DMA Enable Logic |
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Data Rate and Drive Control Registers |
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Swap Drives A and B |
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Non-Burst Mode DMA Option |
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48 Base I/O Address, 15 IRQ and Three
DMA Options |
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Forceable Write Protect and Disk
Change Controls |
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Floppy Disk Available on Parallel Port Pins
(ACPI Compliant) |
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Enhanced Digital Data Separator
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2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates |
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Programmable Precompensation Modes |
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Serial Ports
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Two Full Function Serial Ports |
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High Speed NS16C550 Compatible UARTs
with Send/Receive 16-Byte FIFOs |
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Supports 230k and 460k Baud |
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Programmable
Baud Rate Generator |
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Modem Control Circuitry |
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Infrared Communications Controller
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IrDA v1.2 (4 Mbps), HPSIR, ASKIR,
Consumer IR Support |
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Two IR Ports |
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96 Base I/O Address, 15 IRQ Options
and Three DMA Options |
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Multi-Mode™ Parallel Port with ChiProtect™
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Standard Mode IBM PC/XT, PC/AT, and
PS/2 Compatible Bidirectional Parallel Port |
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Enhanced Parallel Port (EPP) Compatible
- EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) |
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IEEE 1284 Compliant Enhanced Capabilities
Port (ECP) |
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ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-On |
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192 Base I/O Address, 15 IRQ and
Three DMA Options |
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LPC Bus Host Interface
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Multiplexed Command, Address and
Data Bus |
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8 Bit I/O Transfers |
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8 Bit DMA Transfers |
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16 Bit Address Qualification |
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Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems |
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PCI nCLKRUN Support |
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Power Management Event (nIO_PME)
Interface Pin |
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100 Pin TQN, lead-free RoHS compliant package and 100 Pin STQN, lead-free RoHS compliant package |
General Description
The SMSC LPC47N227 is a 3.3V PC 99 and ACPI 1.0b compliant
Super I/O Controller. The LPC47N227 implements the LPC interface,
a pin reduced ISA interface which provides the same or better
performance as the ISA/X-bus with a substantial savings in
pins used. The part also includes 29 GPIO pins.
The LPC47N227 incorporates SMSC's true CMOS 765B floppy disk
controller, advanced digital data separator, 16-byte data FIFO,
two 16C550 compatible UARTs, one Multi-Mode parallel port with
ChiProtect circuitry plus EPP and ECP support and one floppy
direct drive support. The LPC47N227 does not require any external
filter components, is easy to use and offers lower system cost
and reduced board area. The LPC47N227 is software and register
compatible with SMSC's proprietary 82077AA core.
The true CMOS 765B core provides 100% compatibility with
IBM PC/XT and PC/AT architectures and provides data overflow
and underflow protection. The SMSC advanced digital data separator
incorporates SMSC's patented data separator technology allowing
for ease of testing and use. The LPC47N227 supports both 1Mbps
and 2Mbps data rates and vertical recording operation at 1Mbps
Data Rate.
The LPC47N227 also features a full 16-bit internally decoded
address bus, a Serial IRQ interface with PCI nCLKRUN support,
relocatable configuration ports and three DMA channel options.
Both on-chip UARTs are compatible with the NS16C550. One
UART includes additional support for a Serial Infrared Interface
that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats
(used by Sharp and other PDAs), as well as Consumer IR.
The parallel port is compatible with IBM PC/AT architectures,
as well as IEEE 1284 EPP and ECP. The parallel port ChiProtect(
circuitry prevents damage caused by an attached powered printer
when the LPC47N227 is not powered.
The LPC47N227 incorporates sophisticated power control circuitry
(PCC). The PCC supports multiple low power down modes. The
LPC47N227 also features Software Configurable Logic (SCL) for
ease of use. SCL allows programmable system configuration of
key functions such as the FDC, parallel port, and UARTs.
The LPC47N227 supports the ISA Plug-and-Play Standard (Version
1.0a) and provides the recommended functionaity to support
Windows '95/'98 and PC99. The I/O Address, DMA Channel and
Hardware IRQ of each device in the LPC47N227 may be reprogrammed
through the internal configuration registers. There are 192
I/O address location options, a Serialized IRQ interface, and
three DMA channels.
ORDERING INFORMATION
Order Numbers:
LPC47N227-MT for 100 Pin TQN, Lead-free RoHS Compliant Package
LPC47N227-MV for 100 Pin STQN, Lead-free RoHS Compliant Package
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 LPC47N227
Data Brief, Application Notes,
Drivers and Design Tools
| Description |
File Name |
File Size |
Date |
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| LPC47N227 Data Brief |
47n227db.pdf |
90K |
3/29/07 |
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| Evaluation Board |
| EVB-LPCNIO227 |
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| Reference Design
Files |
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| SMSC IrDA NDIS 5.0 Driver for Windows 98,
Windows 98SE, Windows Me, and Windows 2000 |
irndisk.zip |
94K |
9/14/00 |
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| Other Information |
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| Anomaly |
Contact your local SMSC representative |
| Object Code |
Unlimited royalty-free distribution
rights when offered with SMSC controller |
| Source Code |
Contact your local SMSC representative |
| Using the Adobe™ Acrobat™ Reader |
aacrobat.html |
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