LPC47N237
3.3V I/O Controller for Port Replicators and Docking Stations

	LPC47N237 General Description
	Data Brief and Design Tools

Features

	3.3 Volt Operation (5 Volt Tolerant)
	32 SMBus-Hosted General Purpose Input/Output Pins SMBus Slave Controller Enables Read/Write Access to GPIO Ports SMBus Runs on and GPIO Pins Are Driven by Suspend Supply (VTR) SMBus Interrupt Pin SMBus Isolation Circuitry
	PC99a/PC2001 Compliant
	ACPI 1.0b/2.0 Compliant
	Power Management Interface
	LPC Interface Multiplexed Command, Address and Data Bus Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems nIO_PME Pin for UART Ring Indicate PCI Clock Run Support
	Four LPC-Hosted General Purpose Input/Output Pins
	Serial Port Full Function Serial Port High Speed NS16C550A Compatible UART with 16-Byte Send/Receive FIFOs Programmable Baud Rate Generator supports 230k and 460k Baud Modem Control Circuitry 480 Address and 15 IRQ Options Ring Indicator Wakeup Event
	Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Extended Capabilities Port (ECP) ChiProtect Circuitry for Protection 480 Address, Up to 15 IRQ and Three DMA Options
	XNOR Chain
	100 pin TQFP lead-free RoHS compliant package

General Description

The LPC47N237 is a 3.3V (5V Tolerant) PC99a/PC2001 and ACPI 1.0b/2.0 compliant Docking I/O controller. The device, which implements the LPC interface, includes I/O functionality. The LPC47N237's LPC interface supports LPC I/O and DMA cycles. There is also a SMBus hosted GPIO Block.

The LPC47N237 provides four LPC general-purpose pins (GPIOs), which offer flexibility to the system designer. The legacy I/O included in the LPC47N237 are: a 16C550A compatible UART, one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47N237 incorporates sophisticated power control circuitry (PCC) which includes support for PME. The PCC supports multiple low power-down modes.

The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47N237 may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels.

The SMBus hosted GPIO Block includes 32 GPIOs that are powered by standby supply. The GPIOs can be used to assert an interrupt on a change in state of a GPIO. These events are indicated on the nSMBINT pin.

Data Brief and Design Tools

Description	File Name	File Size	Date
LPC47N237 Data Brief	47n237db.pdf	96K	3/30/07