LPC47N267
100 Pin LPC Super I/O with X-Bus Interface

Data Brief and Design Tools

Features

	3.3 Volt Operation (5V Tolerant)
	Programmable Wakeup Event Interface (IO_PME# Pin)
	SMI Support (IO_SMI# Pin)
	GPIOs (29)
	Four IRQ Input Pins
	X-Bus Interface Supports up to Four External Components Supports I/O Cycles (No Memory Support) 8-Bit Data Transfer 16-Bit Address Qualification Write Protection for Each Component
	XNOR Chain
	PC99 and ACPI 1.0b Compliant
	100 Pin STQFP Package
	Intelligent Auto Power Management
	2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports One Floppy Drive Directly Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers Swap Drives A and B Non-Burst Mode DMA Option 48 Base I/O Address, 15 IRQ and Three DMA Options Forceable Write Protect and Disk Change Controls
	Floppy Disk Available on Parallel Port Pins (ACPI Compliant)
	Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes
	Serial Ports Two Full Function Serial Ports High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry
	Infrared Communications Controller IrDA v1.2 (4 Mbps), HPSIR, ASKIR, Consumer IR Support Two IR Ports 96 Base I/O Address, 15 IRQ Options and Three DMA Options
	Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On 192 Base I/O Address, 15 IRQ and Three DMA Options
	LPC Bus Host Interface Multiplexed Command, Address and Data Bus 8-Bit I/O Transfers 8-Bit DMA Transfers 16-Bit Address Qualification Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PCI nCLKRUN Support Power Management Event (IO_PME#) Interface Pin
	Mechanical Package 100 Pin STQFP (12mm x 12mm Body Size)

General Description

The SMSC LPC47N267 is a 3.3V PC 99 and ACPI 1.0 compliant Super I/O Controller. The LPC47N267 implements an LPC interface, a pin reduced ISA interface, for supported I/O and DMA cycles. In addition, this part includes an X-Bus interface that may be accessed through the LPC interface for supported I/O cycles (memory cycles are not supported by this device). The X-Bus interface supports as many as four external components and it offers three different modes of operation for interfacing with these components. The X-Bus interface has an added "Write Protect" feature that ensures that the Base Address and disable bit for each component can only be set by the BIOS to prevent corruption by any virus software. This part also includes 29 GPIO pins.

The LPC47N267 incorporates SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16-byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support and one floppy direct drive support. The LPC47N267 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The LPC47N267 is software and register compatible with SMSC's proprietary 82077AA core.

The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology allowing for ease of testing and use. The LPC47N267 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate.

The LPC47N267 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN support, relocatable configuration ports and three DMA channel options.

Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp and other PDAs), as well as Consumer IR.

The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the LPC47N267 is not powered.

The LPC47N267 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The LPC47N267 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs.

The LPC47N267 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionaity to support Windows '95/'98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each device in the LPC47N267 may be reprogrammed through the internal configuration registers. There are 192 I/O address location options, a Serialized IRQ interface, and three DMA channels.

Data Brief and Design Tools

Description	File Name	File Size	Date
LPC47N267 Data Brief	47n267db.pdf	214K	1/3/05