Introduction

This document is a collection of frequently asked questions regarding the SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface.

Q.	How does the USB3300 control the HostDisconnect bit found in the ULPI RXD command byte? The host disconnect bit is asserted only in Hi-Speed Host mode when a device is disconnected. Here's how it works. The end of packet delimiter (EOP) for the host start of frame packets (SOF's) is a 40bit long sequence of J's or K's. The USB3300 PHY has a comparator that samples the 32nd to 36th bit times of the EOP. If an enumerated device's 45 ohm terminations to ground are not present, the amplitude of the EOP will be approximately 800 mV indicating a disconnect and the HostDisconnect bit will be asserted. If the 45 ohm device terminations are present, the EOP amplitude will be approximately 400 mV and the HostDisconnect bit will not be asserted. The PHY will queue an RXD command byte with the state of the HostDisconnect bit once HostDisconnect has been asserted. This is done so the HostDisconnect assertion won't be missed. It is important that the USB3300 be placed in exactly the HOST Hi-Speed mode called out in the ULPI rev 1.1 specification table 24. In device mode, HostDisconnect will never assert. In device mode, the link is required to examine LineState to detect a disconnect. The USB3300 operates in this way to avoid contention between FS links that use LineState and the PHY.
Q.	Do I have to write to the interrupt enable registers to get HostDisconnect? No, you do not have to enable the host disconnect interrupt registers. The default values of the interrupt enables are to enable both rising and falling edge interrupts.
Q.	Why does HostDisconnect only work in Hi-Speed mode? In previous (UTMI) links, Full Speed disconnect was generated in the link by observing LineState. If the Link and PHY both do Full Speed disconnect and a difference occurred, there would be ambiguity as to which was the correct value. This would have the added problem that if a USB packet was received in this condition the Rxactive would be overloaded by HostDisconnect. The ULPI specification requires that HostDisconnect and Rxactive are mutually exclusive.
Q.	When choosing a power switch to control Vbus in Host or OTG applications, what parameters are important to consider? The switch chosen should provide short circuit protection, and it should prevent back drive when in the off state even if the +5V source is not present. Also, the sense of the on/off control should be considered. The POR state of the CPEN signal from the USB3300 is low. If the switch is active low, Vbus will be on at power up. Most commonly the user will choose a switch with an active high control input. Of course, the switch should be capable of supporting the expected current to be drawn from it. Some switches provide a fault indication output; be sure to use a pull-up resistor on this signal if the switch output is open collector/drain.
Q.	How do I coordinate power-up between the ULPI controller and the USB3300? This is an important consideration; according to the ULPI specification, a non-zero state on the data bus during power-up could be interpreted as valid information causing the PHY to transmit erroneous data. Two ULPI signals controlling the coordination between PHY and link are "DIR" and "STP". The ULPI "DIR" signal is an output from the USB3300 and will be asserted at power-up until the PHY is ready for synchronous operation. The ULPI "STP" signal will hold the PHY in a safe mode state when continuously asserted by the link. There is an on-chip pull-up resistor on STP in the PHY. Generally, the PHY power-up sequence will be much faster than a link's. If the endpoint controller is configured to asynchronously assert STP by default at power-up, the PHY will wait for the link until the link is prepared to begin operation. If a fast link is ready before the PHY, it need only wait for the de-assertion of DIR before beginning operation.
Q.	How is device attachment/detachment detected? A USB device detects an attach when the VBUSVALID (session Valid for OTG devices) bit is set in the RxEvent field of the RXCMD byte. A USB host detects an attach when the LineState bits in the RXCMD byte indicate that either DP or PM has been pulled up. Any change of LineState, Vbus Comparators, or ID will cause an Rx Cmd to be transmitted to the LINK.
Q.	Is it possible to switch On/Off the DM and DM Pull-up resistors? Yes, the Function control register has the Termselect bit in bit [2] and opmode[1:0] bits in bits [4:3]. As seen in table 41 of the ULPI specification (table 6.8 of USB3300 data sheet), Term select controls the DP or DM pull-up as needed in FS and LS operation. All connections to DP/DM can be tri-stated by setting OPMODE[1:0] = 01.
Q.	Where can I find detailed timing illustrations depicting operation of the ULPI bus during USB reset including FS connect, Chirp K, Chip JK, etc.? USB reset and other Bus operations are detailed in the ULPI specification (Downloadable Zip File - 2649K).
Q.	During bus suspend, are there any suggested ways to keep power dissipation low? Power savings mechanisms have been incorporated in the USB3300 that reduce power in suspend mode. This is accomplished by disabling the Interrupt Rise and Interrupt Fall bits for the Sessionend and vbusvalid comparators. See the USB3300 data sheet section 3.1.9.4 for details. Also, the pull-up resistor on the STP input can be disabled to save power. This pull-up is controlled by the Interface control register, InterfaceProtectDisable bit (bit7). See the USB3300 data sheet section 6.1.9.3 for details.
Q.	How is the USB3300 resumed when the clock is not ON? See the section "Exiting Low Power Mode" in the ULPI specification. Briefly, the LINK should asynchronously assert STP and hold it until the CLKOUT signal is turned on and the DIR signal de-asserts. STP is applied asynchronously (because there is no clock at the time) but must be de-asserted synchronously to the CLKOUT signal.
Q.	Does the CLKOUT signal have any glitches when the PHY is coming out of suspend or at power up? No, there are no gliches on entering or exiting low power mode when using the USB3300 PHY.The USB3300 does not turn on the external clock until it is stable and ready for normal operation. DIR will deassert when the clock is stable and accurate to +/- 500 ppm.
Q.	Are there any issues that the user needs to be aware of in order to satisfy the Hi-Speed USB2.0 inter-packet delay time specification? The USB3300 has the lowest RxEndDelay of any PHY period. The USB2.0 specification is 63 Hi-Speed clocks and the USB3300 RxEndDelay is 43 Hi-Speed clocks. This gives the LINK decision time of 16 CLKOUT clock edges so Hi-Speed turn-around timeout is not a problem.
Q.	What is the timing budget for accessing the PHY registers during normal operation? Won’t accessing the PHY registers take bandwidth away from normal data traffic? Accessing the PHY registers does not occur once USB packets begin to be transmitted and received so there is no budget required for this activity in bandwidth calculations.
Q.	The traditional UTMI PHY interface had all status signals available to the link at all times; ULPI requires bus status information to be sent over the same data bus as normal data in the form of an "RX CMD" byte. Can there be conflict or is there a chance of register corruption if a receive packet arrives when the link is writing to a PHY register? The USB3300 has circuits that protect its register contents should the PHY have to interrupt a Link register write to transfer a Received Packet or an RX CMD. In the course of extensive testing with multiple link vendors, SMSC has not seen any problems of this nature. Potential users of the USB3300 should not be the least concerned with this. The ULPI specification accounts for all situations of this nature.
Q.	What should be done with the EXTVBUS input of the USB3300 when operating in peripheral only mode? In peripheral mode, the EXTVBUS PHY input pin should be unconnected (i.e. left floating).
Q.	What needs to be done after the reset bit in register 4 is set? How can it be determined when the reset is complete? The reset bit will be automatically cleared by the USB3300. No action is required by the link controller. DIR will be asserted during the reset process, once DIR de-asserts, the reset process is complete.
Q.	After exiting the low power state (by asserting STP) does the link have to set the SUSPENDM bit in the function control register? No, the USB3300 will automatically set the SUSPENDM bit in the function control register as it exits the low power state.